The use of caches in conjunction with processors has been shown to be very effective in speeding up the rate that instructions are executed. The cache is a memory which is relatively small compared to main memory but which is very fast. The cache is used to provide very fast access to the instructions and/or data which are frequently used. There may or may not be separate caches for instructions (or code) and data. Whether the information is actually instructions or data, the information can be referred to as simply data. There has developed circuitry for keeping track of data which is contained in the cache. The common approach has been to use what is commonly known as TAGs as part of the cache to aid in identifying a request for data or an instruction which is contained in the cache. The processor submits a request for data or an instruction in the form of an address. The TAG is used to determine if the address generated by the processor is one for which the cache has the needed data. The TAG has TAG locations for storing TAG addresses for which information is contained in the cache. The address generated by the processor is compared to the TAG addresses. If the processor-generated address is also a TAG address, then the cache does have the requested data. When this occurs it is generally considered a "hit". When there is a miss in the cache, there is then an access to main memory. The information accessed from the main memory is returned to the processor and the cache stores this information in a data memory and the corresponding TAG address in a TAG location. Least recently used (LRU) logic determines which TAG location is the one that should be replaced by the most recent address which missed in the cache. The replaced TAG location is the one which the LRU logic determined was the least recently used TAG address.
A cache may have, in one extreme, completely fixed addresses which is known as a "direct-mapped" cache. If the TAG addresses are fixed, then there is no need to keep track of the least recently used TAG address because the TAG addresses are fixed. The information which corresponds to the TAG address is the only thing which can be updated. The determination of a hit on the TAG address is very simple because the TAG addresses are hard wired. In another extreme, any TAG location can have any address generated by the processor. In such a case, the determination of a TAG address hit requires reading all of the stored TAG addresses and performing a comparison of each of them with the address generated by the processor. This type of cache is known as a fully associative cache. There is a compromise approach in which certain of the TAG locations can have limited variability. There may be, for example, sets of four TAG locations in which each of the four TAG locations within a set has some bits in common and some that are variable. The common address bits (which comprise what is known as the " index") are thus hard-wired so that in response to an address generated by the processor, one set of four TAG locations is accessed. In such a case, the address generated by the processor can be considered to have an index portion and a TAG portion. The four TAG addresses present in the four TAG locations accessed by the index portion of the processor-generated address are read and compared to the TAG portion of the generated address. If one of the TAG addresses in the accessed TAG locations and the TAG portion of the generated address are the same, then there is a TAG hit. If the data which corresponds to the hit TAG location is valid, then the hit signal is generated and the information which corresponds to the hit TAG location is provided to the processor.
A cache provides a significant improvement in the performance of a processing system but there are number of potential needs. One potential need is for scratch pad operations. Another need is the ability to maintain coherency for the case in which the main memory is shared by a second processing system which accesses the main memory via a secondary bus. Another typical need is to have a memory management unit which translates between logical and physical addresses. It is desirable to achieve these functions as fast as possible while occupying as little board space as possible. Placing more functions on a single integrated circuit is one way of achieving reduced board space. Not all systems, however, require the same functions or in the same degree. For example, scratch pad needs can vary widely. A large number of systems will not have a second system accessing memory on a secondary bus. Thus, placing a large number of different functions on a single integrated circuit may result in a device which is very complex and thus too expensive for many applications. One way this can happen is to excessively proliferate the number of pinouts of the integrated circuit. Thus, there is needed an efficient way of providing different cache, scratch pad, coherency, and MMU related functions for a processing system.